1. Field of the invention
The present invention relates to a serial peripheral interface (SPI) memory module and a control method thereof. In particular, it relates to a SPI memory module using address cache and a control method thereof.
2. Description of the Related Art
The serial peripheral interface (SPI) in wide use nowadays uses different constant bit lengths to transmit control commands (8 bits), 24-bit addresses and then data bits, as shown in FIG. 1. However, when chip select signals are continuously enabled and associated addresses are continuous as well, 24-bit addresses are required to be transmitted repeatedly. As a result, the overall transmission efficiency is reduced and it fails to meet the bandwidth requirement for current high-speed transmission system.
In a general system with a cache, each time the chip select signal is enabled, the amount of accessed data is equal to a cache line size, typically ranging from 16 to 64 bytes. When the chip select signal is continuously enabled, the probability that its corresponding address is also continuous is about 80%˜90%. Accordingly, if the number of transmitting the 24-bit address can be reduced, the speed of data access will increase.